The present invention relates to a sample and hold device with a MOS capacitor.
The prior art essentially discloses two types of sample and hold devices which use MOS technology.
The first type of device comprises a standard MOS transistor, whose source receives the input voltage to be sampled and whose gate receives a sampling voltage. The drain of the MOS transistor is connected to a storage capacitor and to a voltage follower stage with a high input impedance, which can be constituted by two MOS transistors in series. The storage capacitor is not a MOS capacitor. It can be integrated into the semiconductor substrate in which are integrated the MOS transistors, but has two metal plates. The charges are transferred from a MOS transistor drain to the storage capacitor by a connection existing between the drain and one of the plates of the storage capacitor.
The second type of device comprises a MOS transistor having two gates. The gate which is nearest to the MOS transistor source is the sampling gate receiving the sampling voltage, and is followed by an insulating gate raised to a constant potential. The MOS transistor drain is connected, as in the previous case, to a storage capacitor, which is not a MOS capacitor, and to a voltage follower such a MOS transistor, with four electrodes is sometimes called a tetrode type MOS transistor.
The performances of sample and hold devices are essentially defined by two characteristics. One is the acquisition time of each new voltage sample taken from the input voltage of the device and which should be as short as possible. The second is the stray coupling capacitance between the sampling gate and the MOS transistor drain of the device, which should be reduced to the minimum.
Attempts to improve one of these characteristics often leads to a deterioration of the other. Thus, in the prior art sample and hold devices based on MOS technology with a conventional MOS transistor, it is necessary to increase the value of the storage capacitance to reduce the effect of the tray coupling capacitance. The disadvantage is that at the same time the acquisition time is increased.
There are three essential causes for the stray coupling capacitance. The first is the overlap between the sampling gate and the drain diffusion of the MOS transistor. The second is the coupling between the sampling gate and the MOS channel of the MOS transistor. During the passage of the sampling voltage from high level to low level, part of the carriers of the channel is restored to the source and drain diffusions. During this restoration, the drain which is a high impedance point undergoes a potential drop from Q.sub.c /C, in which Q.sub.c represents the restored charge quantity and C the storage capacitance value. Conversely, during the passage of the sampling voltage from low level to high level, the drain gives charge, which raises its potential. The final cause of the stray coupling capacitance is the coupling of the sampling gate of the MOS transistor to the drain via the substrate, which does not have a zero resistance.
In the prior art sample and hold devices based on MOS technology with a MOS transistor having two gates there is no longer an overlap between the sampling gate of the transistor and its drain diffusion, due to the insulating gate. However, the coupling between the sampling gate and the MOS channel of the MOS transistor still exists. The length of the insulating gate of the MOS transistor is increased to reduce the extent of the discharge or restoration undergone by the transistor drain. The disadvantage is that the acquisition time is simultaneously increased.
Thus, with the prior art MOS sample and hold devices, it is difficult to have both a satisfactory acquisition time and a satisfactory stray coupling capacitance.